Minimizing transistor size in order to keep up with Moore's law continually requires reducing first level interconnect (FLI) pitch and bump size. In addition, using advanced dielectrics has often resulted in utilizing low-k and extremely low-k materials in silicon.
The combination of these factors results in higher sensitivity to stress during assembly and thermo-mechanical stress. Therefore, with each new technological advancement, solutions for reducing thermo-mechanical stress become significantly more important.
With the advent of smaller form factor devices (cellphones, tablets) and their short life expectancy, the reliability requirements for such semiconductor packages has reduced. However, high performance large packages still require good reliability performance because such devices typically have an estimated end life of 5-7 years.
Reliability related fails for large die products, especially due to wide area inter layer dielectric (ILD) delamination and fillet cracks, have increased due to the use of low-k and ultra-low-k ILD materials. Current server products barely meet existing reliability requirements. In addition, many users of large electronic packages require strong reliability performance, especially in harsher physical environments.
FIG. 1 shows ILD delamination 1 that is commonly observed in large die electronic packages 2. This type of ILD delamination 1 in such electronic packages 2 typically occurs due to the stresses that are associated with temperature cycling (TC).
As shown in FIG. 1, this type of ILD delamination 1 is a well-known reliability fail mechanism that initiates from one of the corners 3 of the electronic package 2. The conventional solution to prevent such fails is by improving the properties of the underfill material. However, improving the mechanical properties of the underfill comes with compromises on other desirable properties (e.g. flowability and/or cost).
FIG. 1 shows that as the electronic package 2 gets larger, the corners 3 of the electronic package 2 have the highest distance to neutral point DNP, which results in the highest stress being at the corners 3 of the electronic package 2. Therefore, a need exists for a relatively large electronic package that has good reliability performance under a variety of thermal cycling conditions due to reducing the stress on the corners of the relatively large electronic package.